1. Field of the Invention
The invention relates to communication systems, and more particularly to a multi-queue single-FIFO scheme for quality of service (QoS) oriented systems.
2. Description of the Related Art
With the convergence of communication and computing technology, processing platforms have been integrated with communication systems to provide enhanced service features and resource allocation. Such a processing platform is typically coupled to a communication network and hosts several processes for transmitting data to or receiving data from nodes on the communication network. A processing platform may be configured to allocate resources to provide a quality of service (QoS) for particular communication service supported by the processing platform.
A processing platform integrated as part of a communication system may include a peripheral device coupled to a communication medium and a host system to receive data from the peripheral device and transmit data to the communication medium through the peripheral device. A peripheral bus typically transfers data between the host system and the peripheral device. The processing platform that supports QoS and resource allocation typically uses multiple queues in which each queue is associated with a particular QoS requirement and/or a particular data flow. These queues should be effectively processed per their respective priorities, for example, to permit many data flows to be individually scheduled per their respective negotiated QoS levels.
As far as is known, most conventional peripheral devices carry out QoS guarantees over multiple first-in-first-out (FIFO) buffers, i.e., they employ many FIFO buffers to service multiple queues. The FIFO buffer is usually implemented with registers or memory units that occupy the majority of an IC (integrated circuit) chip area. Therefore, the geometry of an IC chip increases as it includes more FIFO buffers. Unfortunately, the larger the chip size, the more costs and power consumption are incurred. Accordingly, there is a need to address such problems of the related art. It would be desirable to provide a multi-queue system with reduced number of FIFO buffers, thereby accomplishing overall system cost effectiveness.